1. Field of the Invention
The present invention generally relates to the fabrication of field effect transistor (FET) structures and particularly to the fabrication of field effect transistor structures with lightly-doped drain (LDD) regions. More specifically, the present invention relates to a method for in-line monitoring of the width of lightly-doped drain regions in the fabrication of lightly-doped drain field effect transistors and offline electrical measurements of the width of the lightly-doped drain regions.
2. Description of the Related Art
Lightly-doped drain (LDD) regions have commonly been used in reducing the length of the channel region in a FET, thereby reducing the size of transistors. The reduction in the length of the channel region is made possible by LDD regions which separate the drain and source regions from the channel region, and thus increase the channel breakdown voltage and reduce electron impact ionization (hot electron effects) by reducing the electric field at the source and drain pinch-off regions.
FETs having LDD regions are typically fabricated by first implanting regions at both ends of a gate with a light dose of an N-type dopant, thereby defining a channel between two N.sup.- regions. A spacer (or mask) is then formed over portions of the N.sup.- regions adjacent to the gate structures. Thereafter, a second implant is performed with a heavier dose of an N-type dopant to form N.sup.+ source and drain regions. The spacer masks the underlying N.sup.- regions during the second implantation so that these regions become the LDD regions Thus, the width of the spacers defines the width of the LDD regions.
While the channel breakdown voltage of a LDD FET and its ability to resist hot electron effects can be increased by increasing the width of the LDD regions, the LDD regions can increase the resistance of the transistor channel and degrade the current drive capability of the FET. Consequently, it is important to control the fabrication process so that an optimum LDD width is achieved.
To control the fabrication process, it is desirable to have a convenient method of monitoring the width of the spacers which mask the N.sup.- regions during the source and drain implant. Two methods are conventionally utilized:
The width of the insulators can be observed cross-sectionally with a scanning electron microscope (SEM). However, this technique, which involves a destructive cleaving of a sample which is then viewed with a SEM, is slow, tedious and cannot be used inline in the fabrication process. The number of samples examined is relatively small because of the inconvenience and the destructive nature of the test. Moreover, the accuracy of this method is limited by the resolution of the SEM.
An electrical method for measuring the width of LDD insulators is described in "Using The Cross-Bridge Structure To Monitor The Effective Oxide Sidewall-Spacer Width in LDD Transistors," by T. Y. Huang, IEEE Electron Device Letters, Vol. EDL-6, No. 5, May 1985, pages 208-210. In this method, the insulator width is determined by measuring the resistance of a region created in a process-monitor wafer having a crossbridge test pattern. In order not to obscure the width information of the cross-bridge test pattern, the N.sup.- implant, which is normally required for LDD formation, is deliberately skipped in the process monitor wafer. Therefore, the method must be practiced on a separate test wafer and cannot be used in-line.